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MP4652 high performance off-line tv led dri ver MP4652 rev.1.0 1 www.monolithicpower.com 1 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. the future of analog ic t echnology descri ption the mp465 2 is a h i g h -performan ce, off-line l e d d r i v e r desig ne d t o pow er led s f o r h i g h - power isolat ed applications, su ch as lcd tv backlight ing. it is availa ble in a 16 -pin soic package. the mp 465 2 can op er ate at a fix ed ope rat i n g freq ue ncy o r a variab le f r eq uen cy co nt ro lled e x t e r n a l l y . it outputs two 180-degree phase- shifted driver signals for various ext ernal power stages, like llc, half bridge and flyback. its enhanced 9v gate driver can sufficiently drive the external mosfets and dire ctly drives the external gate drive transformer. the mp465 2 implemen ts fast and continuous pwm dimming for le ds. it outp u ts a drive r signal to dir e ctly dim the led current through a dimming mosfet an d achieves fast pwm dimming. it provides continuous gate driver signals to t he power stage to the whole pwm dimming cyc l e that eliminates the au dible noise: the MP4652 can a c hieve 1000:1 p w m dimmin g ratio without any audible noise issue . the pw m dimming is controlled by either a dc input voltage or a direct pw m signal. t he dc input pwm dimmi ng frequency can be synchronized by an extern al signal. the b u ilt - in f a u l t man a gemen t fe at ure s inclu de ope n led pr ote c t i o n , shor t le d pro t e c t i o n , prot ection a gainst sh ort s along any po in t o f th e led str i n g to gr oun d, an d ove r temp era t ur e prot ection . t he p r o t e c t i o n inte rf ace is flexib le an d i s ea s y t o use . at f au l t p r o t ec ti on , s y st e m c a n be set u p w i th a u to- r e c overy or la t c h up. features ? llc, half bridge or flyback controller ? fast and continuous p w m di mmin g with audible noise elimination ? 1000:1 pwm dimming ratio ? input voltag e range from 9v to 30v ? 9v enhanced gate driver ? fixed or ext e rnally programmable operating frequency ? dc or pw m input dimming control ? dc input pwm di mmin g frequency synchronization ? smart fault protection i n terface ? open and short led string protectio n ? protection against short s along the led string to ground ? built-in fault manageme n t ? system aut o recovery or latch up at fault protection ? available in soic 16 pa ckage ? pin-to-pin with mp4651 appli c ations ? flat-panel video displays ? street lighting for mps g reen sta t us, plea se v isit mp s w ebsite under q uality assuran c e . ?mp s ? and ?th e fu ture o f a nal og ic t e chno lo gy ? are r e g i ste r ed t r a dem ar ks o f monolithic pow e r sy st em s , inc. the MP4652 is covered by us pa ten t s 6 , 683,422, 6,316,8 81, and 6,114,814. other pa tents pending. http://
MP4652?high performance o ff-line tv led dri ver MP4652 rev.1.0 1 www.monolithicpower.com 2 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. simplified typical application vin en pwm 400v gnd 400 v ref ref ovp 1 10 11 12 5v* (see note) ocp pwmout pwm o u t syn c en fb vc c bf s fs e t ft gn d gl pwm o u t vi n gr ov p pwm i n co m p 1 2 3 4 5 6 7 8 9 MP4652 13 14 15 16 ssd ovp1 ocp 400v g n d . . . . . . ovp2 ovp 2 ref fcomp fcomp ir e f MP4652 ll c application: recommended for pwm dim m ing frequencies from 100hz to 2khz *note: the 5v could be an accurate reference voltage generated from a tl431. vin en di m 400v gnd 4 00v ref ref fb ovp 10 11 12 fb ocp pwm out pw m ou t sy n c en fb vc c bf s fs e t ft gn d gl pw m o u t vi n gr ov p pw m i n co m p 1 2 3 4 5 6 7 8 9 MP4652 13 14 15 16 ssd sync sync syn c ovp ocp 400v gnd . . . half bridge application: recommended for pwm dimmi ng frequencies greate r than 2khz
MP4652?high performance o ff-line tv led dri ver MP4652 rev.1.0 1 www.monolithicpower.com 3 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. ordering information part number* package top marking free air temperature (t a ) MP4652es soic16 MP4652es -20c to +85c * for tap e & reel, ad d suf f ix ?z (e.g. MP4652es?z ) for rohs co mpliant pa ckaging, ad d su ffix ?lf (e.g. MP4652es? lf?z ) package reference ovp sync ssd fb gr gnd gl vcc 1 2 3 4 16 15 14 13 vin en pwmin bfs 12 11 10 9 comp ft pwmout fset 5 6 7 8 top view pin 1 id absolute m a xi mum ratings (1) input voltag e v in .......................................... 35v vcc, gl, gr ............................. -0.3v to +10.7v fb, ssd ....................................... - 5.8v to +5. 8 v other pins .................................... - 0.3v to +6. 5 v continuous power dissipation (t a = 25c) (2) ???? ? ???? ? ???? ? ???.1.56 w junction te mperature ............................... 150c lead temperature (solder)....................... 260c operating frequency .............. 20khz to 15 0khz storage temperature ............... - 55c to +150c recommended operating conditions (3) input voltag e v in ................................. 9v to 30v maxi mum j unction temp. (t j ) .................. 125c thermal resistance (4) ja jc soic16 ................................... 80 ...... 35 ... c/w notes : 1) exceeding these ratings ma y da m age the device. 2) the maximum allowable power dissipation is a function of the maximum junction temperatur e tj(max), the junction-to- ambient thermal resistance ja, and the ambient temperature ta. the maximum allowable c ontinuous power dissipation at any ambient temperature is calculated by pd(max) = (tj(max)-ta)/ ja. exceeding the maximum allowable powe r dissipation w ill cause ex cessive die tempe r ature, and t h e regulator w ill g o into thermal shutdo w n . inte rnal thermal shutdo w n circuitr y pr otects the device from permanent damage. 3) the device is not guarant eed to function outside of its operating conditions. 4) measured on jesd51-7, 4-layer pcb
MP4652?high performance o ff-line tv led dri ver MP4652 rev.1.0 1 www.monolithicpower.com 4 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. electri c al characteristi cs v in = 12v, t a = 25c, u n less otherw i se noted. parameter symbol condition min typ max units gate driver gl, gr gate pull- do wn r e si stan c e r gd 2 ? gate pull- up re sista n c e r gu 4 ? output source curre n t i sour ce 1 a output sink curre n t i sink 2 a maximum duty cycle d m ax 46% en en turn on thre sh old v en-on 2 v en turn off thres h old v en-off 1 v internal pull-down res i s t or r en-in 60 k ? brightness dimming control range (pwmin) pwm full scale v pwm dc input pwm dimming 1.1 1.2 1.3 v pwm logic input threshold v th-pwm pwm dimming 1.6 1.9 2.2 v pwm logi c input hyste r e s is v t h-p w m -hy st pwm dimmin g 0.1 v burst frequency set (bfs) source curre n t i src(b f s) v bfs = 2v 120 140 170 a lower threshold v v(bfs) 2.2 2.4 2.6 v upper threshold v p(bfs) 3.3 3.55 3.8 v supply current supply cu rre nt (enable d ) i in-en no drive r out put 1.5 2.5 ma supply cu rre nt (disable d ) i in-off v in = 30v 1 a operating frequency f o 25k ? fset to gnd 46.5 50 53.5 khz frequency set voltage v fset 1.14 1.2 1.25 v output pwm dimming signal for led (pwmout) logic high voltage v h-pwmout normal operation 5 6 6.5 v logic low voltage v l-pwmout at fault cond ition, 25k ? fset to gnd 0.1 0.6 v output pwm source curre n t i sour ce_pw m out 100pf o n pwmout pi n 3 ma output pwm sink cu rrent i sink_ p w m out 100pf o n pwmout pi n 20 ma led current feedback (fb) magnitud e |v fb | 0.57 0.6 0.63 v input re sista n ce r fb_in 30 k ? over voltage protection (ovp) over voltage protectio n thre sh old v t h (ovp) 2.22 2.38 2.55 v
MP4652?high performance o ff-line tv led dri ver MP4652 rev.1.0 1 www.monolithicpower.com 5 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. electri c al characteristi cs (continued) v in = 12v, t a = 25c, u n less otherw i se noted. parameter sy mbol conditio n min t y p max units fault timer (ft) thre sh old v th(ft ) 2.2 2.4 2.6 v source curre n t i sour ce(ft ) 8 a com p clamp volta g e v co m p 0.60 v referen c e current i co m p + fb = 0v 20 a pull down cu rre nt at fault condition i co m p- f ault fault mode i s triggered 30 a burs t freq u e nc y s y nchroniza tion (s ync) high l ogi c le vel v s y nc-h 1.4 v low l ogi c le vel v s y nc-l 0.7 v pulse width t sy n c 6 20 s synchroni zin g freq uen cy f sync dc input pwm dimming, comp ared to the freque ncy f bfs s e t by bfs pin r an d c 110% 120% f bfs fault dete ction threshold (ssd, fb) ssd thres hold v ssd 2.22 2.36 2.55 v ssd dete ctio n delay time t d_ssd 7 s fb thre shol d v fb 1.1 1.2 1.3 v fb detectio n delay time t d_fb 7 s vcc voltage v vcc no loa d 8.7 9.7 10.5 v cur r e n t i vcc 20 ma
MP4652?high performance o ff-line tv led dri ver MP4652 rev.1.0 1 www.monolithicpower.com 6 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. pin functio n s pin # name description 1 ovp over voltag e prote c tion. t he outp u t voltage i s sen s e d by this pin t h rou gh a voltage divid e r. if the voltage at ovp exceeds 2.38v for 7 s, the fault mode is triggered. 2 sync synchronization. for burst dimming frequency. a pplication of a narrow-pulse synchronizing signal on this pin will synchronize the burst frequency on bfs pin. the frequency of the synchronizing signal should be higher than the frequency set by bfs pin. 3 ssd short string dete ction. a comp arator i s integrate d in this pin for short st ring p r otection. if the voltage on this pin falls below 2.36v for 7s, the fault mode is triggered. 4 fb led cu rre nt feedba ck i nput. the averag e voltage at this pin is regul ated to 0.6v by a n internal error amplifier. the voltage on this pi n is also u s e d fo r sh or t string detectio n . when the volta ge on thi s pi n goe s high er t han 1.2v fo r 7s, the ic reco gni ze s this a s short string condition and trig ge rs the fault mod e . for fixed-op e r ating?f req u e n cy pwm-co ntrolled ap pli c ation s ? s u c h as half-b r id ge, flyback o r other topolo g i es? s h unt a current-sen sing resi st o r from the catho de of the led to groun d and u s e a sample -hold ci rcuit to feed the led cu rrent to fb pin. the sa mpl e -hol d ci rcuit sho u ld hold t he se nsed cu rre nt value on fb pin at pwm off interval. for frequ en cy controlled appli c ation s , like the ll c topology, the led curre n t is regul ated through an external amplifier, pull fb to ground and let ic operate with maximum duty cycle. 5 comp feedb ack co mpen sation nod e . for fixed-o p e r at ing ? frequ en cy pwm-co ntrolle d appli c ation s , con n e c t a co mpen sation capa citor o r an r-c n e two r k from this pin t o gnd. for frequency controlled applications, like the llc topology, connect a 1nf cap on this pin. 6 ft fault timer. con n e c t a timing ca pa citor from this pin to gnd to s e t the fault ti mer to recover the syste m . whe n the vo ltage on thi s pin go es higher th an th e 2.38v thre shol d, the ic r e covers . if the system requires a latch up for fault mode, connect a resistor smaller than 250k ? to this pin. 7 pwmout pwm dimming control output. this pin outputs the pwm dimming driver signal to the led dimming mosfet for fast pwm dimming. in fault mode pwmout is pulled low. 8 fset freq uen cy set. the source current through th is pin determine s the operating f reque ncy of the MP4652. for fixed - op e r ating?f req u e n cy pwm - co ntrolled appl i c ation s , conn ect a re sisto r from thi s pin to gnd to set the op erat ing fre que ncy. for typical appli c ation s , a 25 k ? re si st or set s t h e operating fre quen cy at 50 khz. for fre quen cy controlle d a pplication s (li k e ll c) , ap pl y the control voltage (the output of the regul ation lo op) to this p i n throug h a resi st or. thi s co ntrol volt age prog ram s the so urce curre n t throu gh the fset pin and thu s controls the o peratin g freq uen cy. 9 bfs burs t frequenc y set. for dc input pwm dimmin g . conn ect a resi sto r in p a rallel with a cap a cito r fro m bfs to gnd. the re si stor and cap a ci tor pro g ra ms the burst freq uen cy. for direct pwm input pwm dimming, pull up bfs to vcc with a 20k ? resistor and apply the pwm signal to the pwmin pin. 10 pwmin pwm dimmi ng cont rol input. for dc i nput pwm di mming, the voltage ra nge from 0 v to 1.2v at pwmin linearly sets the pw m di mming duty cycle from 0 to 100%. for direct pwm input pwm dimming, directly apply the pwm signal on this pin. the MP4652 has positive dimming polarity.
MP4652?high performance o ff-line tv led dri ver MP4652 rev.1.0 1 www.monolithicpower.com 7 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. pin functio n s (continued) pin # nam e description 11 en enable input. pull en high to turn on th e chip, and pull en low to turn it off. 12 vin supply voltage input. 13 vcc linea r reg u l a tor output and bias supply of the gate driver. it provide s the supply for the gate drive r a nd also the e x ternal co ntro l circui t, the typical value i s 9.7v. bypass vcc with a 1 f or lar g e r cer a mi c ca pa cit o r. 14 gl driver signal output, 180 degree phase shifted from gr 15 gnd ground. 16 gr driver signal output, 180 degree phase shifted of gl
MP4652?high performance o ff-line tv led dri ver MP4652 rev.1.0 1 www.monolithicpower.com 8 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. block diagram ovp fb fset co m p 1 4 5 8 0.6v 2.38v ssd 3 2.36v pulse width modulation pwmin 10 pwmout 7 driver en 11 ft 6 2.38v gr 16 ga te driver gl 14 vin 12 regulator vc c 13 gm 1.2v dc l/ r bfs 9 sync 2 burst dimming signal generator fault management figure 1?MP4652 bl ock diagram
MP4652?high performance o ff-line tv led dri ver MP4652 rev.1.0 1 www.monolithicpower.com 9 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. operation stead y state and enable control the mp465 2 is a h i gh- performance, off-line l e d driver specifica lly designed for high-power isolated ap plication s such as led backlighting for tvs. powered by a 9v to 30v input supply, the mp465 2 outputs two 180-degree phase - shifted gate driver sig nals for ex ternal power stages. it s enhanced 9v gate driver provide s adequate driver capability to the external mosfets and dire ctly drives the external mosfets t h rough a gate drive transformer. the MP4652 ca n be used to control ll c, half-bridge, flyback, and other power stages. the mp465 2 can accu rately regulate the led output curr ent using b o th pwm control and a compensation network on the comp pin. p w m con t ro l u s e s an ext e rn al re sist or co nne ct ed fro m f s e t p i n t o g n d to set the operating frequency. the led current feeds back to the fb pin with a sample-hold circuit an d compared against an internal 0.6v reference voltage. the compensation network on the comp pin, which connects to the output o f the error a m plifier, the n accurately regulates the output led current. the voltage on comp pi n is compared with the internal o s cillator and generates duty cycl e modulated signals to control the e x ternal power switches. t h is pwm control makes MP4652 suitable for half-bridge, flyback, and other power stages. the mp465 2 fset pin can also take volta ge feedback fr om a frequ ency-controlled external circuit to a d just the device frequency. conn ect this feedba ck circuit to fset using a resistor . this freque ncy control makes mp4 652 suitable for llc an d other fre quency-controlled powe r stages. the sy stem power is co ntro lled by en p i n. w h en the chip is ena ble d , t h e bu ilt- in re gu lat o r fo r vc c power s up t he in ter n a l circu i t . whe n vcc exceed s it s uvlo point, ic sta r t s t o op era t e an d ou tpu t s th e gat e d r ive signa ls. brightness control MP4652 i m plements pwm dimmin g on the led current by using either a dc input voltage or a direct pwm input sign al. the MP4652 has a built-in bur st oscillator that can generate a triangle waveform on the bfs pin. when using a dc i nput voltage for pw m dimming, connect a capacitor in parallel to a resistor on bfs pin to set the bu rst frequency and apply the dc voltage to the pwmin pin t o program the pwm dimming duty cycle. the burst fr equency ca n also be synchronized t o an external freque ncy by applying a synchronizin g narrow-pulse signa l o n the sync pin. the synchronizin g frequency should be higher than the burst fr equency set by the bfs pin. please refer to s y nc pin description f o r details. when using a direct pwm input signal for pwm dimming, u s e a 20k ? pull-up resistor between the bfs pin to vcc and apply the pwm signal on pwmin pin. continuous fast pwm dimming the MP4652 implements fast and continuous pwm di mmi ng on the l e d current, as shown in figure 2. the pwm di mming signal (controlled b y a dc input voltage or a direct pwm signal) outputs fro m the pwmout pin to drive t h e external dimming mosfet in series with t he led string. therefore, the led current quickl y rises when the pwm dimming sign al goes high, and quickly falls when p w m dimmin g signa l fa lls. this fast pwm dimming feature helps t he MP4652 achieve a high pwm dimming ratio. the MP4652 provides continuous p w m dimmin g to the syste m . it output s cont inuou s gate dr iver signals to th e power stage during both pwm o n and pwm off intervals. this makes the pow er flow continu ous for mag netic components?such as transfor m ers and inductor s ?which can eliminate audible noise . with this f a st and co ntinuous p w m dimmi ng feature, the MP4652 can achieve 1000:1 hig h
MP4652?high performance o ff-line tv led dri ver MP4652 rev.1.0 1 www.monolithicpower.com 10 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. pwm dimming ratio at a 120hz p w m dimmin g frequency without any audible no ise issue ( o r 500:1 pwm dimming ratio at 300hz pw m dimming fre quency). pwmout i led pwmin comp ga t e figure 2? fast and continuous pwm dimming fault protection system fault management features include op en led protection, short l e d protection if at any point the le d string sho r ts to groun d, protection against shor ts along the led string, and a dela y timer for system recovery. the output voltage is monitored by the ovp pi n through a voltage divider. once the open led condition occurs and the voltage o n the ovp pin exceeds 2.3 8 v for 7 s, the MP4652 recognize s this a s ope n condit i on and tr igge rs the fault mode. the ssd pin monitors t he secondar y side curre nt. if any point of the led string is short ed to groun d, the seconda ry side current increase s . when the voltage on ssd pin falls below 2.3 6 v for 7 s, the MP4652 triggers the fa ult mode. the fb pin can also fun c tion as sho r t led string protection. when the voltage on f b pin is hig her than 1.2v for 7 s, the ic triggers the fault mode. in fault mo de, the outp u ts of the g a te drivers gl and gr are disabled, the pwmout signal is pulled low, and the comp capacitor is discharged by a 30 a current sour ce. the f ault timer then starts. an 8 a current so urce charge s the ft capacitor, and when ft voltage hits 2.38 v, the system recovers. the ic enables the output driver signa ls, relea s es the comp, resets the fault flag, an d pulls down the ft pin. if the de sig n requires a latch up for the ic at fault mode, connect a 200k ? resistor on the f t pin.
MP4652?high performance o ff-line tv led dri ver MP4652 rev.1.0 1 www.monolithicpower.com 11 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. appli c ation information pin 1 (ovp) : this pin is used for over-voltage protection. when the output volta ge to th is pin exceed s 2.38v for 7 s, the fau lt mode is t r iggered. fo r application s involving multiple led strings, a pply the maximu m output vol t age of the l e d strings t o this pin. pin 3 (ssd) : this short string detection pin is used for protection a gainst short s along any point of th e led string t o ground. t he ssd pin monitors th e secondary side current. when the voltage on this pin falls below 2.36v f o r 7 s, the ic treats t h e condition a s a short and triggers the fault mode. pin 4 (fb): this pin is used for le d current re gulation. th e voltage on this pin is r egulated by an external circuit with a 0.6v average value. use a samp le- hold circu i t to sense th e led current when the pwm goes high, and hold the value when th e pwm goes low. the fb pin also functions as short string protection. when the voltage on fb excee d s 1.2v for 7 s, the ic triggers the fault mode. for frequency-controlle d applicat io n like an ll c power stage, the led current is regulated with an external-frequency control loop. connect fb to ground and set the ic to operate at the maxi mu m duty cycle. pin 5 (comp): this pin is use d for co mpensat io n purp o ses. f o r pwm-co ntr o lled ap plicat ions, su ch a s h a lf-b ridge and f l yba ck pow er st age s, con n e ct a n x 7 r c e r a m i c c a pa ci t o r wi th a va lu e be t w e e n 47 n f an d 4 7 0 n f f r o m c o m p t o g n d . the value of this capacitor d e termines t he stability of the led current regu lation. for frequency-controlled applicat ions like t h e llc power stage, conn ect a 1nf capacitor to t h e comp pin. pin 6 (ft): connect a capacitor from this pin to gnd to set the fault timer. this sets the system recovery time after detecting a fault condition. a c v t ft ft p 8 38 . 2 u a 10nf cap a citor on f t sets the delay time to around 3ms if the circu i t requires a latch-up for fault mode, connect this pin to a 200 k ? resistor. pin 8 (fset ): this pin is used to set the operating frequency. the source current thr ough this p i n determines the operatin g frequency. for fixed-operating?fre quency pwm-controlled application s ?like ha lf-b ridge and flyback power stages?con nect a resistor from this pin to gnd to set the o perating fre quency (f o ). the value for this resi stor r fset is calculated by o fset f r 9 10 25 . 1 u for an ope rating frequ ency of 50khz, r fset = 25k ? . for frequency-controlle d applicatio ns like ll c, connect the control volt age to fset pin throug h a resistor, as shown in figure 3. this contr o l voltage programs the so urce current through this pin to contro l the operating frequency. fset i ref i led m p 46 52 v control figure 3?fset set up for frequenc y controlled application.
MP4652?high performance o ff-line tv led dri ver MP4652 rev.1.0 1 www.monolithicpower.com 12 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. pin 7 (pwmout): this pin o u tputs the pwm dimming signa l t o drive the dimming mosfet in series with the led string for fast pwm dimming. connect this pin to the g a te of the dimming mosfet through a driver resistor. pin 10 (pwmin): this pin is used for pwm-dimmi ng brightne ss control. for dc-input pwm dimming, the d c voltage cont rols the pw m dimming duty cycle o n the out put. t he si gnal sh ould be filt ered f o r op ti mal operation. a voltage in t he range of 0v to 1.2v o n pwmin pro g rams the pwm di mmi ng duty cycl e from 0 to 100%. for direct pwm input pwm dimmin g , pull bfs high to vcc throug h a 20k ? resistor, and connect the pwmin pin directly to the pw m source. logic high is pwm on and logic low is pwm off. pin 9 (bfs): bfs pin is u s ed to set th e burst freq uency for dc input pwm dimming, us ing the waveform shown in figure 4. connect a resistor (r bf s ) in paralle l with a capa citor (c bfs ) on this pin t o set t he bu rst frequency. bfs 2.4v 3. 5 5v b ur s t di mm i ng s i gn al i le d b urst dimming frequency rising time gat e figure 4?pwm dimmi ng w i th dc input voltage at pwmin pin these values are deter mined as follows: set a percentage of the rising time, where: burst rise rise f t d u r bfs and c bfs are determined by: k d k r rise bfs 43 . 21 1 1 16 . 21 ? ? 1 ? | 405 . 0 1 u u bfs burst rise bfs r f d c for d rise = 0.1, f burst = 200hz, then r bfs = 2 12k ? , c bf s = 52nf. d rise is r e commended between 0.1 and 0.2. for direct p w m input pwm dimming, pull bfs high to vcc through a 2 0 k ? resistor and apply the pwm signal to pwmin pin. pin 2 (sync): this pin is used for burst frequen cy synchroniza tion to synchronize th e dc input pwm di mmi ng frequency. application of a small- pulse synchronizing frequency signal will synchronize the burst fr equency. sy n c en fb vc c bf s fs e t ft gn d gl pwm o u t vi n gr ov p pwm i n co m p 1 2 3 4 5 6 7 8 mp 4652 14 15 16 ss d 10 11 12 s y nc si g n a l 9 re f 13 a bfs i le d bu r s t di m m i ng s i g nal 1. 2 v 3. 55v 2. 4 v sync s i gnal a figure 5?sy nchronize d dc input pwm dimm ing and schematic
MP4652?high performance o ff-line tv led dri ver MP4652 rev.1.0 1 www.monolithicpower.com 13 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. figure 5 sh ows synchronized pw m dimming with dc input. the synchronizing signal is filtered by a high pass filt er. its rising edge is cau ght and use d to synchronize the trian g le waveform on the bfs pin. the synchronizin g frequency should be higher than that set by bfs pin and the amplitude of the synchronizing sign al should b e higher than 1.4v. table 1?function mo de pin connec t ion function pwmin bfs sync pwm dimming with dc input voltage *0v to 1.2v c bfs , r bfs gnd pwm dimming with dc inp u t voltage and synchronizing frequency *0v to 1.2v c bfs , r bfs r,c,d netwo rk pwm dimming with dire ct pwm i nput pwm to vcc throug h 20k ? resi st o r gnd note : *: burst brightne ss polarity : 100 % dut y c y cle at p w m voltage 1.2v. pin 11 (en): pull this pin high to enable the chip, and pull it low to disable the chip. pin 12 (vin): supply volta ge input. bypass the su pply voltage with a 0.1 f or larger ce ramic capacitor pin 13 (vcc): this pin pro v ides the gate driver supply voltage. its typical va lue is 9.7v. connect a 1 f or greate r ceramic capacitor to this pin to bypa ss the supply voltage. this voltage is also used to supply th e external control circu i t. pin 14(gl), pin 16 (gr): gate driver signals outp u t. gl and gr are 180 - degree phase-shifted d r iver signals. gl and gr can directly drive the external mosfets in the off-line syst em through a gate drive r transformer with enhanced driver capability. connect two 5.1 ? resist ors in series with gl and gr to reduce the emi noise. place a 2.2nf y capacitor between the primary reference ground and the second ary referen c e ground.
MP4652?high performance o ff-line tv led dri ver MP4652 rev. 1. 01 www.monolithicpower.com 14 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. exam ple appli c ation tv led ba cklight this app lication example introduces a high performance 2-stage l l c tv led driver that is designed to power the led backlights for a 40- inch tv. the total system power structure is shown in figure 6. it uses a 2-sta ge structure with high eff i ciency and low cost. th e pfc stage outputs aro und 390v and is cont rolled by th e mps pfc controller mp44010, which works in bcm (boun dary conduction mode). the MP4652 acts a s the led driver stage: it controls a ll c power stage to drive t he led strings. another flyback dc/dc stage outputs the 13v powe r supply for the system: it uses the mps quasi- resonant flyback contro ller hfc0100. p f c s t age mp44010 ac input le d d r i v er s t age MP4652 llc . . . led strings fl y b a c k d c / d c hfc0100 13v/3a p f c _3 90v . . . figure 6?sy stem pow e r structure the followin g introduces the detailed circuit of th e led driver stage ba sed on m p 4652. the specification s for this le d driver are listed below. specification: input: typically 390v, pfc output. output: 4 strings at 55v/260ma per string , connecting 2 strings in series. it co uld also out put 2 strings at 110v/260ma per string. operating frequency: ~110khz pwm dimmi ng frequency: 320hz protection: open led protection, short led string protection, short l e d+ to gnd protection schematics: figure 7 shows the schematic of the led dri v e r stage. the parameters of the powe r transformer t2 are as follow: np: ns = 6 5 :35, leaka ge inductan c e = 450 h, magnetic in ductance = 1.6mh.
MP4652?high performance o ff-line tv led dri ver MP4652 rev. 1. 01 www.monolithicpower.com 15 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. figure 7?MP4652bas ed 2-stage llc tv led drive llc power stage open protection led current regulation MP4652 short protection system error signal
MP4652?high performance o ff-line tv led dri ver MP4652 rev. 1. 01 www.monolithicpower.com 16 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. pow e r stage the power stage is a half-bridge llc topolog y. the primary side is co mposed of q4, q3, c19 and t2. the llc reson ant network is compose d of the lea k age inducta nce of t2, the magnetic inductance of t2, and c19. q4 and q3 should be chosen to handle the input voltage and the llc current. consider the operating frequency, the input condit i on and the output con d ition when selecting t he resonant cap, the leakage inductance, and the magnetic indu ctance. refer to MP4652 llc design notes for det ails. on the secondary side, the diodes d6, d8, d9, and d10 rectify the ll c current. these diod es must be able to handle the output voltage an d the output current: they are 200v/ 3 a diodes in this circui t. the balance cap c23 blocks the different voltage of th e 2 led strings and balances th e currents t h rough them. the valu e of c23 is usu a lly between 0.22 f and 1 f. its voltage mu st be highe r than the output voltage because of the led string short co ndition. the output capa citors c28 and c29 filt er the ripple current of th e llc outp u t current to obtain a dc current for the led strings. c28 and c29 also store the e nergy from the primary side at t h e pwm off interval, as MP4652 implemen ts continuous gate driver at pwm off interval to eliminate th e audible noise. the value of c2 8 and c29 must be large enough to handle this energy to prevent excessive output voltage spikes: cap a citor value s from 4.7 f to 22 f a r e typical for this applicat ion. the volt age stress of these output capacitor s should be higher than th e maxi mum o u tput voltage. control circuit MP4652 controls the p o wer mosf ets q3 and q4 in the p o wer stage through th e gate driv er transformer t1. as MP4652 outputs regulated 9 v gate driver signals, the turn ratio of t1 goes fro m 1:1:1 to 1:1.5:1.5. with its enhanced gate driver capability a nd regulate d driver voltage, mp465 2 can direct ly drive the mosfets through the ga te driver transformer. because an llc is a frequency-controlled power stage, MP4652 uses a n external amplifier u3 to regulate th e led cu rrent and output t h e frequency control volta ge. during t he pwm on interval, pwmout is high an d the dimming mosfet q8 turns on. the led current feeds back to th e inverting input of u3. with t h e compensation network, u3 outputs t he frequency control voltage and regulates the led current. during the pwm of f interval, the dimmi ng mosfet tu rns off, and led curre nt feedback goes low. an external voltage applied to t h e inverting input of u3 through d5 pu lls the outpu t of u3 low. this design h e lps the circuit work at a high frequency during t he pwm of f interval an d limits the output energy delivered from t h e primary side to the seco ndary side. together with the output capacitor s c28 and c29, this cir c uit helps to eliminate current overshot during pwm on. the signal mosfets q6 and q7 are turned off durin g the pwm off interva l , and c21 an d c24 can hold their value during this time. this helps the control loop to respon d quickly during the pwm on inte rval and to achieve fast pwm dimming. r35 and c1 2 on the fs et pin form a frequency soft-start cir c uit at start up. the maxi mu m output vol t age is fed back to ovp pin through the voltage dividers. MP4652 ca n protect the open led condition thro ugh the ovp pin. when t he voltage on ovp pin i s higher tha n 2.38v for 7 s, ic enters fault mode. the second ary side current is fed back to ssd pin through r47, r46 and c25. when sho r t condition o ccurs, the secondary side curren t grows and the ssd voltage falls. when ssd voltage falls below 2.36 v for 7 s, t he ic enters fault mode. in fault mode, the pwmout pulls low. the device then outputs an error signal to the system with the addition of an external logic circuit,. please refer to the design notes for details of the components selection.
MP4652?high performance o ff-line tv led dri ver MP4652 rev. 1. 01 www.monolithicpower.com 17 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. circuit performance stead y state start up 90 % pw m dimming 50 % pw m dimming 1 % pw m dimming 0.2 % pw m dimming gl vled i pri 1.13i led gl vled i pri 1.13i led gl v led 1.13i led i pri gl v led 1.13i led i pri gl v led 1.13i led i pri gl v led 1.13i led i pri
MP4652?high performance o ff-line tv led dri ver MP4652 rev. 1. 01 www.monolithicpower.com 18 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. le d c u r r en t vs . p w m d u t y c y cl e 0 50 100 150 200 250 300 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% p w m du t y cy c l e l e d cu r r en t(m a) pwm dimming linearity open led protection sho r t led+ to led- prote c tion short led+ to gnd protection gl ssd ishort error gl vled i pri error gl ssd ishort error
MP4652?high performance o ff-line tv led dri ver notice: t he i n formatio n in this docum ent i s subject to chang e w i t h o u t notice. users sh oul d w a rra nt and gu arante e that third part y int e ll ectu al prop ert y r i g h ts are n o t inf r ing ed u p o n w hen i n tegr atin g mps product s into an y ap p licatio n. mps w i ll not assume a n y le gal res pons ib ili t y for an y sai d app licati ons. MP4652 rev. 1. 01 www.monolithicpower.com 19 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. package informati o n soic16 0.016(0.41) 0.050(1.27) 0 o -8 o detail "a" 0.010(0.25) 0.020(0.50) x 45 o see detail "a" 0.0075(0.19) 0.0098(0.25) 0 .150 ( 3.80) 0 .157 (4.00) pin 1 id 0.050(1.27) bsc 0.0 13(0. 33) 0.0 20(0. 51) seating plane 0.0 04(0. 10) 0.010(0.25) 0.38 6( 9.8 0) 0.394(10.00) 0 .053(1 .35) 0.069(1.75) top view front view 0.228 (5.80) 0.244 (6.20) side view 1 8 16 9 recommended land pattern 0.213 (5.40) 0.063 (1.60) 0.050(1.27) 0.024(0.61) note: 1) control d i mension is in i nches. d i mension in bra cket is in millimeter s. 2) pac k age len g t h does not incl ude mold fl ash, protru sion s or ga te bu rrs. 3) pac k age widt h does not in clu d e int e rlea d flash or protru sion s. 4) l e ad copl anar ity ( bottom of leads a f t e r formin g) shal l b e 0 .004" in ches ma x. 5) dr awing confor ms to jedec ms-012, variat ion ac . 6) dr awing is not to scal e. 0.0 10(0.25) bsc gauge plane

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